Until now, IP cores delivered to customers were mainly targeted for in-flight applications. This means that no errors are allowed to be generated from the system.
However, a recent customer application required Mil-Std-1553 testing capabilities from an already-existing flight system, so that the same system can be used as a bus simulator on the ground or as an in-flight operational system.
Multi-RT feature is an essential feature for a Mil-Std-1553 bus simulator. It means that a single 1553 node can be programmed to act as many 1553 remote terminals. The user can program the Remote Terminal (RT) addresses, which are simulated and thus the unit will answer and create messages, as requested by a Bus Controller (BC) for the simulated RTs.
The Error Injection feature enables the system to simulate several types of errors which may occur on a 1553 network. Therefore, errors like Parity Error, Sync. Error, Zero-Crossing Error and others are all part of an advanced 1553 test and simulation system.
Same hardware for interface card and test bench
Many avionics vendors, who develop avionic systems, are required to provide test benches for their systems. In many cases, developing the test bench is an expensive project, requiring development of boards, software and other simulation tools, usually at low volumes. Therefore the advantages of developing a single hardware that can be used both as a flight system and as a bus simulation tool are obvious. First – there is only the need to develop a single hardware, and not require equipment from additional vendors for bus simulation and testing. Second – customers can re-use the software written originally for the actual system also for testing, ensuring lower development cost and enabling faster time to market.
Of-course, the customer needs to make sure that the test software is not loaded into the operational systems. This can be achieved by having a separate FPGA load file for each system and also by enabling or disabling the multi-RT and Error Injection features by hardware. This means that the IP core can enable or disable the features, by reading hardware configuration bits, which are set differently between the tester and the in-flight system.
Both features can be added to Sital’s standard Mil-Std-1553 IP core and are provided with software API, so that users can easily implement these test features into an existing Mil-Std-1553 system.
More information about Sital Technology’s Mil-Std-1553 products can be found at: www.sitaltech.com/.