Thales had 38 patents in cybersecurity during Q3 2023. One patent focuses on protecting circuits from timing attacks by adding a random delay and situating the circuits in a single chip housing to interfere with each other. Another patent involves a method for installing a service worker firewall on a web browser and applying rules to cross-origin requests. Additionally, Thales SA has patented a system for tracking user activity using API key mapping to tokens. Lastly, there is a patent for a protected circuit that includes multiple identical circuits hosted in a common chip-housing and a physical barrier to prevent physical access, with impedance changes indicating attempts to breach the barrier. GlobalData’s report on Thales gives a 360-degreee view of the company including its patenting strategy. Buy the report here.
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Thales grant share with cybersecurity as a theme is 63% in Q3 2023. Grant share is based on the ratio of number of grants to total number of patents.
Recent Patents
Application: Protected circuit system and method of operation (Patent ID: US20230214536A1)
The patent filed by Thales SA describes a protected circuit system that aims to prevent timing attacks by adding a random delay to the signals transmitted between integrated circuits. This random delay is preferably implemented within the protected volume and can be achieved using random delay buffers, such as random shift-registers. The system also suggests situating the circuits in a single chip housing to make it difficult to obtain information from the signals by causing interference. Additionally, a physical barrier can be used to limit physical access to the circuits, with the barrier having an impedance (e.g., capacitor, resistor, inductivity) that can detect any changes beyond a chosen threshold, indicating an attempt to physically destruct or enter the barrier. Suitable actions can be taken upon detecting such changes, such as deleting information, destroying the chip, or providing wrong information. The barrier can also act as a reflector, making it difficult to obtain information from the desired signal of the chip.
The patent claims describe various aspects of the protected circuit system. Claims 1-8 focus on the timing interface of the system, which introduces a variable delay to the signals and transmits them to their intended destination. The variable delay can be random or pseudo-random and can be added at different levels (protocol mode or signal mode). Claims 9-11 describe a configuration where multiple integrated circuits with a common function and a communications interface are used, with one circuit acting as a responder. Claims 12-15 discuss the use of an enclosure with conductive shells and an integrity monitor to detect deviations in the complex impedance between the shells, triggering actions like resetting the circuits or clearing memory. Finally, claims 16-17 cover the method of operating the protected circuit system and a computer program implementing the steps.
In summary, the patent filed by Thales SA describes a protected circuit system that adds random delays to signals to prevent timing attacks. It suggests using random delay buffers, situating the circuits in a single chip housing, and implementing a physical barrier with impedance to limit physical access. The patent claims cover various aspects of the system, including the timing interface, configuration of multiple integrated circuits, and the use of an enclosure with conductive shells and an integrity monitor.
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GlobalData, the leading provider of industry intelligence, provided the underlying data, research, and analysis used to produce this article.
GlobalData Patent Analytics tracks bibliographic data, legal events data, point in time patent ownerships, and backward and forward citations from global patenting offices. Textual analysis and official patent classifications are used to group patents into key thematic areas and link them to specific companies across the world’s largest industries.
